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Project Abstract

It is commonly known that accesses to off-chip resources, particularly memory, cause considerable performance limitations in computing systems. To speed up memory access it is necessary to design high frequency chip-to-chip interconnects. These high frequency connections introduce many second order effects that make bit sampling difficult. It is proposed that current signal analysis techniques are researched and used to develop a software tool that interconnect designers can use to obtain design validation of a given interconnect with a fixed sampling window. It is expected that such a tool will allow designers to develop faster and lossless interconnects.

2008 Team Members

Bryson Kent, u0553461(AT)utah.edu

Ben Meakin, ben.meakin(AT)utah.edu

Jordan Kemp, jordan.kemp(AT)utah.edu

M. Lucas Loero, u0527079(AT)utah.edu

Raheem Alhamdani, R.Alhamdani(AT)utah.edu

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Code Locations:
http://micron-clinic-2008.google...
Licenses:
GPL-2.0+
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Ohloh computes statistics on FOSS projects by examining source code and commit history in source code management systems. This project has code locations but that location contains no recognizable source code for Ohloh to analyze.

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Creative Commons License Copyright © 2013 Black Duck Software, Inc. and its contributors, Some Rights Reserved. Unless otherwise marked, this work is licensed under a Creative Commons Attribution 3.0 Unported License . Ohloh ® and the Ohloh logo are trademarks of Black Duck Software, Inc. in the United States and/or other jurisdictions. All other trademarks are the property of their respective holders.