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NIBZ is a compact innovative microprocessor described in VHDL. The innovation is based around how the machine encodes instructions. There are 16 basic instructions and one advanced call instruction. The advanced call instruction gives the density of direct threaded code with the speed of subroutine threaded code. Certain choices of instruction were purposefully left out. A good example being a literal value load. When threaded code is analyzed, it can be seen that this instruction would not be used very often, as the placement of that value onto a stack makes for extra instructions, loosing code density.
There is an (A)ccumulator and 4 main registers
(P)rogram Counter (the code flow) (Q)uality Register (adds some quality and memory indexing ability easy) (R)eturn Stack Pointer (the threading and route to literal fetching and branching) (S)tack Pointer (for ALU and data operation) This processor is dedicated to the Moores and the more's and the moors.
The 16 basic instructions are encoded in the low nibble of a machine code word. The advanced call instruction is identified by being greater than 15. This has many benefits, including elimination of some branch delay slots in a full pipeline architecture, and effective little-endian load pre-decoding. It must be noted that the memory organization is big endian, even though fetches and stores are done in little endian order.
From NibzX onwards a 3 in 1 opcode compression feature has been added. This uses the lower 16K words to present virtual subroutines of 3 instructions. This is the video area too on the ReferenceSystem and so has no conflict.
The first project phase is complete with a half width data bus for using cheaper memory. This places total instruction fetch and execution time to 5 cycles. The second project phase concentrating on the IO is now in progress.
Phase 1 : Processor Phase 2 : An IO standard (Graphics, Sound, SPI Boot, SD Card, 2*8 Bit Ports) Phase 3 : A Hardware Reference Phase 4 : An Emulator Phase 5 : Multi-processing To Clarify Licence IssuesA one core (single instruction stream execution) per chip (piece of silicon/SOI/GaAs cut to fit a mounting) licence is available for free. This allows use in propritory designs, while still allowing full utility (any number of cores) in open BSD designs. The instruction design is well suited to dataflow multiple dispatch, with the elimination of cycle overheads of stack shuffling.
Have a look at the InstructionSet for more details. The VHDL is OpenSource BSD and the VHDL was produced with the aid of Altera Quartus II. This project will be given a boost by the development of a Forth language system for it. The this is started on Gforth for nibz . A J2MERef java source of the instuction operation is available, to be used in an emulator, although it is quite old and has not been modified to the new instruction timings.
A hardware ReferenceSystem is in the design process.
This is an n+4 design all extension is via n+5, etc.. For an insight on how generalization to programming of Objects will occur, Think Object Transfer Language, although this is a long way off.
Check VersionList for version details and extras. Try WhatIsVHDL too, to see an old version.
The OldDesign indi proessor is now not developed, but the design can be downloaded. The reason for the change is obvious when threaded code is considered.
K Ring Technologies Semiconductor
The Direct Injection Switching Channel Organization (DISCO) FET symbol above is based upon the idea of a parallel channel which charges, but does not conduct, either by doping levels or a thicker oxide layer. The resulting antiphase injection or collection of charge carriers reduces the miller capacitance effect.
"Yet more great technology from K Ring." - Simon Jackson, BEng.
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