Ohloh by Black Duck

 Follow @ Meta   Join Now

 Settings |  Report Duplicate
Activity Not Available
1

News

  Analyzed about 2 years ago based on code collected almost 4 years ago.
 
Update ChangeLog
Posted about 1 month ago by olivier.girard
Rev 187 - olivier.girard (1 file(s) modified)Update ChangeLog~ /openmsp430/trunk/ChangeLog_core.txt
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247
Posted about 1 month ago by olivier.girard
Rev 186 - olivier.girard (7 file(s) modified)Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43
~ ... [More] /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v
~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v
~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v
~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_multiplier.v
~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v [Less]
Update Altera FPGA example bitstream (no functional change... only generated ...
Posted about 1 month ago by olivier.girard
Rev 185 - olivier.girard (1 file(s) modified)Update Altera FPGA example bitstream (no functional change... only generated ...~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.sof
Fixed some project settings for newer Quartus version (12.1)
Posted about 1 month ago by olivier.girard
Rev 184 - olivier.girard (2 file(s) modified)Fixed some project settings for newer Quartus version (12.1)~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.qsf
~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v
Update ChangeLog
Posted 3 months ago by olivier.girard
Rev 183 - olivier.girard (1 file(s) modified)Update ChangeLog~ /openmsp430/trunk/ChangeLog_core.txt
Minor update to reflect new ASIC_CLOCKING option.
Posted 3 months ago by olivier.girard
Rev 182 - olivier.girard (4 file(s) modified)Minor update to reflect new ASIC_CLOCKING option.~ /openmsp430/trunk/doc/html/asic_implementation.html
~ /openmsp430/trunk/doc/html/software_development_tools.html
~ /openmsp430/trunk/doc/openMSP430.odt
~ /openmsp430/trunk/doc/openMSP430.pdf
Update with latest oMSP Core version.
Posted 3 months ago by olivier.girard
Rev 181 - olivier.girard (25 file(s) modified)Update with latest oMSP Core version.~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
~ ... [More] /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v
~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v
~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v
~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v
~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v
~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v
~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v
~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v
~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v
~ /openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite
~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_module.v
~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_register_file.v
~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_sfr.v
~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_watchdog.v
~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v
~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_undefines.v
~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v
~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v
~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v
~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v
~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v
~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v [Less]
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with ...
Posted 3 months ago by olivier.girard
Rev 180 - olivier.girard (29 file(s) modified)Add new ASIC_CLOCKING configuration option to allow ASIC implementations with ...~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
~ ... [More] /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v
~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v [Less]
Update all linker scripts with a simplified version. Thanks to Mihai ...
Posted 3 months ago by olivier.girard
Rev 179 - olivier.girard (2 file(s) modified)Update all linker scripts with a simplified version.
Thanks to Mihai ...~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/linker.x
~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/linker.x
Update all linker scripts with a simplified version. Thanks to Mihai ...
Posted 3 months ago by olivier.girard
Rev 178 - olivier.girard (11 file(s) modified)Update all linker scripts with a simplified version.
Thanks to Mihai ...~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0
~ ... [More] /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.x
~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu
~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.x
~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1
~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.x
~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x
~ /openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x
~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/linker.x
~ /openmsp430/trunk/fpga/altera_de1_board/software/memledtest/link.ld
~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/software/leds/linker.x [Less]
 

 
 

Project Summary

Code Data

SCM Data

Community Data

 

Creative Commons License Copyright © 2013 Black Duck Software, Inc. and its contributors, Some Rights Reserved. Unless otherwise marked, this work is licensed under a Creative Commons Attribution 3.0 Unported License . Ohloh ® and the Ohloh logo are trademarks of Black Duck Software, Inc. in the United States and/or other jurisdictions. All other trademarks are the property of their respective holders.