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BackgroundC/C++ is the language for system engineers to develop the algorithm. VHDL/Verilog is the language for IC designers to develop the hardware. Normally, the C/C++ is translated to VHDL/Verilog by hand. This is tedious and error-prone process. Although industry exists some tools, such as ... [More] Catapult C, Handel-C. They are far from perfect. Purpose of this projectThis project is to develop the tool based on a total different approach, which featuring: - AXI based synchronous handshaking - Resource based; conflicts are automatically resolved useful linkshttp://www.mentor.com/products/esl/high_level_synthesis/catapult_synthesis/index.cfm [Less]

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