Projects

hmc-mips

Harvey Mudd College and The University of Adelaide, Australia A project to create a MIPS microprocessor from Verilog simulation to chip fabrication.

nibz

Donate via Payal NIBZ is a compact innovative microprocessor described in VHDL. The innovation is based around how the machine encodes instructions. There are 16 basic instructions and one advanced call instruction. The advanced call instruction gives the density of direct threaded code with the ... [More] speed of subroutine threaded code. Certain choices of instruction were purposefully left out. A good example being a literal value load. When threaded code is analyzed, it can be seen that this instruction would not be used very often, as the placement of that value onto a stack makes for extra instructions, loosing code density. There is an (A)ccumulator and 4 main registers (P)rogram Counter (the code flow) (Q)uality Register (adds some quality and memory indexing ability easy) (R)eturn Stack Pointer (the threading and route to literal fetching and branching) (S)tack Pointer (for ALU and data operation) This processor is dedicated to the Moores and the more's and the moors. The 16 basic instructions are encoded in the low nibble of a machine code word. The advanced call instruction is identified by being greater than 15. This has many benefits, including elimination of some branch delay slots in a full pipeline architecture, and effective little-endian load pre-decoding. It must be noted that the memory organization is big endian, even though fetches and stores are done in little endian order. From NibzX onwards a 3 in 1 opcode compression feature has been added. This uses the lower 16K words to present virtual subroutines of 3 instructions. This is the video area too on the ReferenceSystem and so has no conflict. The first project phase is complete with a half width data bus for using cheaper memory. This places total instruction fetch and execution time to 5 cycles. The second project phase concentrating on the IO is now in progress. Phase 1 : Processor Phase 2 : An IO standard (Graphics, Sound, SPI Boot, SD Card, 2*8 Bit Ports) Phase 3 : A Hardware Reference Phase 4 : An Emulator Phase 5 : Multi-processing To Clarify Licence IssuesA one core (single instruction stream execution) per chip (piece of silicon/SOI/GaAs cut to fit a mounting) licence is available for free. This allows use in propritory designs, while still allowing full utility (any number of cores) in open BSD designs. The instruction design is well suited to dataflow multiple dispatch, with the elimination of cycle overheads of stack shuffling. Have a look at the InstructionSet for more details. The VHDL is OpenSource BSD and the VHDL was produced with the aid of Altera Quartus II. This project will be given a boost by the development of a Forth language system for it. The this is started on Gforth for nibz . A J2MERef java source of the instuction operation is available, to be used in an emulator, although it is quite old and has not been modified to the new instruction timings. A hardware ReferenceSystem is in the design process. This is an n+4 design all extension is via n+5, etc.. For an insight on how generalization to programming of Objects will occur, Think Object Transfer Language, although this is a long way off. Check VersionList for version details and extras. Try WhatIsVHDL too, to see an old version. The OldDesign indi proessor is now not developed, but the design can be downloaded. The reason for the change is obvious when threaded code is considered. K Ring Technologies Semiconductor The Direct Injection Switching Channel Organization (DISCO) FET symbol above is based upon the idea of a parallel channel which charges, but does not conduct, either by doping levels or a thicker oxide layer. The resulting antiphase injection or collection of charge carriers reduces the miller capacitance effect. "Yet more great technology from K Ring." - Simon Jackson, BEng. Charitable Director and Creative Technologist Phone/Fax/Forwarding: +44 (0)709 289 7191 (yac.com) Phone SMS Only: +44 (0)796 797 3001 (Orange) Phone: +44 (0)1924 635 485 (Tesco Internet Phone) [Less]

bebopframework

http://www.eleves.ens.fr/~barbin/bebop/index.html Bebop Framework est un ensemble de bibliotèques et d'outils logiciels dédié au développement hardware numérique synchrone. Centré autour de son langage de description de netlist, Bebop Framework propose différents modes de simulation ... [More] , transcription, compilation d'architectures matérielles permettant ainsi une certaine interopérabilité avec d'autres univers de développement hardware. Bebop Framework propose également des modules de macro-génération de tests unitaires sur circuits éléctroniques, permettant l'automatisation de vérifications dynamiques sur des propriétés des états logiques des signaux, utilisable dans un mode debug. [Less]

jvex-robotics

Jvex-robotics interfaces Java single board computers to the VEX Robotics Robotics Design System Kit. The goal is to free the Java host from low-level device management by delegating these tasks to the VEX Controller that comes with the kit. The result is that a Java host can easily manage real-time ... [More] VEX devices over a serial protocol. The VEX controller directly manages sensor and motor hardware. Given a decent 'C' compiler, the pair of PIC microprocessors is well suited for offloading low-level, real-time device control from the Java host. The serial protocol incorporates I/O Point Tagging which provides a means for peripherals to characterize themselves via XML descriptors to the host. [Less]

r-vex

ρ-VEX: A Reconfigurable and Extensible VLIW ProcessorThis is the project website for ρ-VEX, an open source VLIW processor with an accompanied development framework. The project started as the MSc project of Thijs van As. About ρ-VEXρ-VEX is an open source reconfigurable and extensible ... [More] Very-Long Instruction Word (VLIW) processor, accompanied by a development framework consisting of a VEX assembler, ρ-ASM. The processor architecture is based on the VEX ISA, as introduced by J.A. Fisher et al.. The VEX ISA offers a scalable technology platform for embedded VLIW processors, that allows variation in many aspects, including instruction issue-width, organization of functional units, and instruction set. The ρ-VEX source code is described in VHDL. ρ-ASM is written in C. A software development compiler toolchain for VEX is made publicly available by Hewlett-Packard. The reasons VEX was chosen as the ISA are merely its extensibility and the quality of the available compiler. The design provides mechanisms that allow parametric extensibility of ρ-VEX. Both reconfigurable operations, as well as the versatility of VEX machine models are supported by ρ-VEX. The processor and framework are targeted at VLIW prototyping research and embedded processor design. The name ρ-VEX stands for 'reconfigurable VEX' processor. Because the letter Rho (P or ρ) is the Greek analogous for the Roman R or r, ρ-VEX is pronounced as r-VEX. This is also the correct spelling when no Greek letters can be used (as is the case with the project website URL). Getting StartedTo start experimenting with ρ-VEX, read the QuickstartGuide and download the latest code snapshot, or checkout trunk. When you have a Xilinx University Program Virtex-II Pro Board by Digilent, you should have ρ-VEX running within moments. DocumentationThijs' MSc Thesis with extensive documentation about ρ-VEX' design and implementation ρ-VEX: A Reconfigurable and Extensible VLIW Softcore Processor (Presented on ICFPT'08) QuickstartGuide OperationsSemantics instruction_layout.txt syllable_layout.txt Contact Information Thijs van As Computer Engineering Laboratory Faculty of Electrical Engineering, Mathematics and Computer Science Delft University of Technology Delft, The Netherlands [Less]

dino-mon

One can say, dino-mon is a kind of quasi-OS prepared for very specific hardware built around the Intel 8085 CPU, It allows the user to change I/O state and to affect memory content, to load additional code as IntelHex records and many others, all of this with support of interactive command ... [More] interpreter. More complex dino-mon commands affect I2C bus devices, on-board serial port and similar stuff. Additionally, it contains a set of system procedures to be used in user (uploaded via serial link) applications. They cover standard LCD module and I2C bus support as well as several general purpose utilities (memory management, dynamic interrupt redirection etc.). All software is written in pure assembly language, free SB-Assembler (by San Bergmans, http://sbprojects.com/) is currently used for development. (olga & natasza) [Less]

arduinobinaryclock

This project contains the schematics and source code to create a binary clock using Arduino.

8051-sim

8051 Simulator

tlcs900archc

ArchC description of the TOSHIBA TLCS900 family of microcontrollers. This description can be used to automaticaly generate binutils tools for this platform. We will initially focus only on description of the instruction set so that we can have a port of the GNU as (assembler). Later we intend to port GCC also.

backtothefutur

Given subject : The 4004 is Intel’s first computer ever. You will implement in Verilog a model of the 4004, interface it to the nanoboard and then make a real 4004 work. Design the 4004 demo board Simulate it on Altium’s nanoboard. Own a real vintage piece to show to your kids.