Projects

vtagspython

IntroductionVtags is an auxiliary tool for verilog coder. It can analyze verilog source code files, and do following two things: . create hierarchical report, which figures out the module instantiation tree. . create tags, which can be used vi VI eidtor. Yes, just like ctags, but with additional ... [More] feature, that can trace signal drivers. Known Issues. python 2.3 or above needed . nested `include directive not supported . limited support for `define directives DownloadTo download vtags by subversion: svn checkout http://vtagspython.googlecode.com/svn/trunk/ vtags.py is built from python, you need a python runtime to run it. You can get your python runtime at this URL: http://www.python.org/download Any comment is welcome: vtags是verilog语言的辅助工具。它读入verilog的源代码，完成两个功能： 生成hierarchy.rpt 这是层次化的，描述模块嵌套调用关系的报表 2.生成tags 这是给vi用的文件，可以实现关键词跳转。 是的，就像ctags。但是比ctags胜在能实现信号驱动关系的追踪。 下载可以用subversion 客户端软件 svn checkout http://vtagspython.googlecode.com/svn/trunk/ 也可以直接用http://下载 http://vtagspython.googlecode.com/svn/trunk/ 该程序是用python写的，要运行它，用户需要先安装python运行环境。你可以在这个地址找到适合你的系统的python： http://www.python.org/download [Less]

hdltags

The perl code (hdltags or vtags) creates tags for verilog/system verilog/vhdl code for browsing the code with functionalities similar to ctags Current version supports Verilog and System-Verilog. VHDL would be supported soon! Only module names are tagged. Usual ctags commands work: vi −t tag ... [More] : Start vi and position the cursor at the file and line where "tag" is defined. :ta tag : Find a tag. Ctrl-] : Find the tag under the cursor. Ctrl-T : Return to previous location before jump to tag (not widely implemented). To download checkout using svn, or send an email to hdltags@anurag-kumar.com -Anurag [Less]