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IntroductionVtags is an auxiliary tool for verilog coder. It can analyze verilog source code files, and do following two things: . create hierarchical report, which figures out the module instantiation tree. . create tags, which can be used vi VI eidtor. Yes, just like ctags, but with additional ... [More]
The perl code (hdltags or vtags) creates tags for verilog/system verilog/vhdl code for browsing the code with functionalities similar to ctags Current version supports Verilog and System-Verilog. VHDL would be supported soon! Only module names are tagged. Usual ctags commands work: vi −t tag ... [More]