Projects

Qucs

Qucs is a integrated circuit simulator for rapid development of analog and digital circuits and wide range of simulations. DC, AC, S-parameter, noise and transient analysis are supported, mathematical equations and use of a subcircuit hierarchy are available. Digital circuit models and ... [More] simulations are supported thanks to integration with FreeHDL and Icarus Verilog. Output is may be presented with wide variety of graph and tabular charts. The package consists of two utilities: Qucs, elegant and powerfull GUI for designing and simulating circuits, with point-and-click interface, based on Qt® by Trolltech®. Qucsator, a command line circuit simulator. It takes a network list in a certain format as input and outputs a Qucs dataset. May also be used by applications other than [Less]

Icarus Verilog

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

Milkymist

The project develops a stand-alone device in a small form factor that is capable of rendering MilkDrop-esque visuals effects in real time, with a high level of interaction with many sensors and using live audio and video streams as a base. Open source components and design tools have been developed ... [More] or used as much as possible. A system-on-chip implemented in a FPGA has been chosen for meeting this goal at the IP core level. The flexibility of the FPGA enables advanced users to modify the design, and also permits compact integration of many interfaces (MIDI, OSC, DMX512, analog sensors, video inputs), making Milkymist™ a platform of choice for the mobile VJ. The design is also highly modular and documented, making the code easy to re-use in other open source system-on-chips. [Less]

openmsp430

The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430 microcontroller family and can execute the code generated by an MSP430 toolchain in a cycle accurate way. The core comes with some peripherals (GPIO, TimerA ... [More] , generic templates) and a Serial Debug Interface for in-system software development. [Less]

vector06cc

This project is a complete open source replica of Vector-06C (Russian: Вектор-06Ц), a retro, Soviet-era home computer, in a FPGA. If you're new to this, fpga4fun is a good place to start learning. Altera DE1 development board with Cyclone II FPGA is the primary development platform. ... [More] The project uses a mixture of Verilog and VHDL code. All original code is written in Verilog, while some of the modules, e.g. T80 CPU and 82C55 PIO controller are written in VHDL. This version of T80 is the most accurate implementation of 8080 to date. The complete set of 8080 Exerciser test results matches that of the real CPU. Make sure to browse the Wiki, GettingStarted is a nice place to start. Also check out the videos of work in progress. Returning users please check Revision_History page for news. Этот проект полностью воссоздает цветной компьютер Вектор-06Ц без зеленых конденсаторов. Весь компьютер, включая процессор и дисковод, помещается в одной микросхеме ПЛИС, а его структура и поведение описаны на языках Verilog и VHDL. Если вы не знаете, что это такое, но хотите узнать, сходите на fpga4fun. Проект разрабатывается на плате Altera DE1. Часть кода заимствована из других открытых проектов. В частности, использованы ядра T80 CPU, 82C55. Используемая в этом проекте версия процессора T80 является самой точной на сегодняшний день реализацией процессора КР580ВМ80А. 100% результатов теста 8080 Exerciser совпадают с полученными на настоящем процессоре данными. Начните с прочтения руководства GettingStarted на Вики. Оно написано на двух языках и содержит ссылки на другие документы. Можно также посмотреть на ютубы снятые на разных стадиях создания компьютера. На странице Revision_History находится журнал версий. [Less]

hdfs

HDFS is a hardware design language embedded in F#. It is based upon, and in some parts compatible with, HDCaml. Features Installation To do Documentation Namespaces Logic design API overview Simulator overview Examples Hello world Counter Adder (and simulation) Fir filter (and waveforms) Xilinx library Behavioral Code

cs3710

The purpose of this project is to create a Verliog-synthesizable simulation of a CR-16 processor with our own special brand of multi-media extension. This project is being done as a semester-long assignment for Erik Brunvand's CS 3710 course at the University of Utah.

fpga-tools

FPGA Software, Tools and IP-Cores

bf533

verilog based DSP processor design

aes-plb-core

AES PLBProject repository for my AES PLB core. This core is designed to be used as a PLB peripheral using the Xilinx Platform Studio. All associated files (user logic and drivers) are (or will be shortly) in the SVN repository. The design of this core is to be as easy to use as possible in the ... [More] wrapper between PLB interface and the AES IP. NOTE: This is a work in progress still, and is not complete. Expect files up by the end of this week (3/19/20008) NEWS5/2/2008 The original IP core I choose relied upon delays for its pre-synthesis simulation to appear to match FIPS197. Obviously, this crashed and burned very badly upon implementation and the discovery that the post synthesis implementation was b0rked. I've choosen a new core and was able to drop it into my existing design with no problems, but am having trouble interfacing my IP into the IPIC interface... 3/19/2008 SVN is difficult to setup for a whole XPS project directory, so I'm probably only going to be hosting the drivers (.c and .h files) and the pcore (user_logic.v & associated AES files) information. There will be the documents needed to successfully import this peripheral into a XPS design. I will be hosting test applications. [Less]