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this project is to explore using python as a the glue to tie multiple instances of the verilog simulation language together, in a multiprocessor configuration. It relies heavily on the pyhvl project at pyhvl.sourceforge.net
This project helps to verify the design in verilog via PLI or VPI. Though PLI is a useful interface, it is a little complex when using PLI directly. CBVM packages PLI routines in C++ so that it can be easily to use.
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